1. Field of the Invention
The present invention relates to an image sensor which has a memory together with photoelectric conversion elements within an identical semiconductor chip.
2. Related Background Art
Generally, as photoelectric conversion systems, there have been various systems in which images are read respectively by image sensors of CCD (charge coupled device) type, MOS (metal-oxide semiconductor) type, bipolar type and the like. For a video camera and the like, a CCD sensor of which image quality is excellent has been frequently used. On the other hand, even in the sensors of latter two types in recent years, SN ratio is improved, low power consumption is realized, and the sensor itself can be fabricated together with its peripheral circuits within one chip thereby realizing downsizing. For these reasons, such the advantages have brought the sensors of these two types into public notice.
Furthermore, it has been proposed in recent years an example that photoelectric conversion elements are assembled into photoelectric conversion blocks whose driving and output conditions can be determined independently. An example of one of the plurality of photoelectric conversion blocks arranged in the image sensor will be explained with reference to FIG. 1. FIG. 1 shows a one-dimensional image sensor. In the drawing, numeral 1 denotes a photoelectric conversion pixel composed of a bipolar transistor 2 and a MOS transistor 3 for resetting the base of the transistor 2. In the pixel 1, a PN junction formed in the base-collection junction region of the transistor 2 is irradiated, and a signal voltage generated by accumulation of electric charges owing to the incident light and the corresponding increase of base potential is output from the emitter of the transistor 2. As shown in FIG. 1, the plurality of pixels 1 are arranged over one line.
Numeral 50 denotes a voltage supply source for resetting the base of the pixel 1, numeral 4 denotes a pixel output line connected to the emitter of the transistor 2, numeral 5 denotes a MOS transistor for resetting the line 4, and numeral 6 denotes a bipolar transistor the base of which is connected to the line 4. The emitter of each transistor 6 in each line is connected to an output line 7 in common. The transistor 6 acts as a means for detecting the maximum value of the photoelectric conversion output, whereby the voltage corresponding to the maximum output voltage of the pixel array is generated from the output line 7.
As above, by connecting the emitters of the bipolar transistors to the output line in common, a maximum voltage detection circuit is formed.
Numeral 8 denotes a storage capacitor for storing the output voltage of the pixel, numeral 9 denotes a switching MOS transistor for performing connection and disconnection between the pixel output line 4 and the capacitor 8, numeral 10 denotes a MOS transistor switch for selecting the capacitor 8, numeral 11 denotes a shift register for outputting the control signal to the gate of the switch 10 to sequentially select the plurality of switches 10, numeral 12 denotes an output line for reading the charges from the selected capacitor 8, numeral 13 denotes an amplifier to which the line 12 is input, numeral 14 denotes an output terminal of the amplifier 13, numeral 15 denotes a comparator for judging the magnitude of the output value from the line 7, numeral 16 denotes a driving control circuit for driving the photoelectric conversion block and also controlling the signal from the comparator 15, and numeral 17 denotes a driving line for, e.g., a clock signal, an inverted clock signal and a start signal to drive the shift register 11. Numerals 18, 19 and 20 denote driving lines respectively for applying gate driving pulses to the gates of MOS transistors 3, 5 and 9, numeral 21 denotes a wiring for supplying a comparison potential to the comparator 15, and numeral 22 denotes a latch circuit for latching the output of the comparator 15.
In the example shown in FIG. 1, the pixel 1, the capacitor 8 and the latch circuit 22 are simultaneously reset. After then, the switch 9 is set to be conductive as maintaining the level of the line 20 high. As the signal charges are accumulated in the pixel 1, the potentials of the line 4 and the capacitor 8 increase. Then, if the output corresponding to the maximum value of the pixel output exceeds the reference potential determined by the wiring 21, the output of the comparator 15 is inverted to switch over the latch circuit 22. Thus, since the level of the line 20 is changed to be low and also the switch 9 is turned off, the signals accumulated up to this time are held by the capacitor 8.
In the image sensor having the plurality of photoelectric conversion blocks as shown in FIG. 1, even in a case where light intensity in each block is different from others, the output values of the blocks can be at about the same level by controlling the pixel signal accumulation time of each block to be different. Although the pixel of bipolar type is shown by way of example in FIG. 1, generally a photoelectric conversion pixel of any type may be used. Furthermore, monitoring of the pixel output is not limited to the maximum value detection. Namely, the detector of minimum value or the detector difference between the maximum and minimum values may be designed.
In the conventional art, any problem does not occur in a case where the number of photoelectric conversion blocks is small and each block is formed at the position separated from others. However, in a case where the number of blocks is large and thus it is necessary to array the photoelectric conversion blocks closely, there is the problem that it is impossible to allocate the space on which the driving control circuit 16 and the shift register 11 are arranged.